The objective in permanent or irreversible bonding of substrates is to produce a connection as strong and as permanent as possible, i.e., a high bond force, between the two contact surfaces of the substrates. For this purpose, in the prior art there are various approaches and production methods, such as the welding of the surfaces at higher temperatures.
All types of materials, predominantly metals, semimetals, semiconductors, polymers and/or ceramics, are permanently bonded. One of the most important systems of permanent bonding is metal-metal systems. Cu—Cu systems have appeared increasingly in recent years. The development of 3D structures requires the joining of different functional layers. This joining is more and more often accomplished by way of so-called TSVs (through silicon vias). The contact-making of these TSVs with one another very often takes place by copper contact sites. At the instant of bonding, there are very often full-value, serviceable structures, for example microchips, on one or more surfaces of the substrates. Since different materials with different coefficients of thermal expansion are used in microchips, increasing the temperature during bonding is not desirable. This can lead to thermal expansions and thus to thermal stresses and/or stress induced voiding (SIV) which can destroy parts of the microchip or its vicinity.
The known production methods and the approaches which have been followed to date often lead to results which cannot be reproduced (or can only be poorly reproduced) and which can hardly be applied to altered conditions. In particular, production methods which are used at present often use high temperatures, especially >400° C., in order to ensure reproducible results.
Technical problems such as high energy consumption and a possible destruction of structures which are present on the substrates result from the high temperatures which have been necessary to date for a high bond force and the rapid and/or often completed temperature changes which arise due to loading and/or unloading, of in part far above 300° C.
Other demands consist in the following:    back-end-of-line compatibility.
This is defined as the compatibility of the process during the processing. The bonding process must therefore be designed such that back-end-of-line structures, generally consisting of electrical conductors and low-k dielectrics which are already present on the structure wafers, are neither adversely affected nor damaged during the processing. Compatibility criteria include mechanical and thermal loadability, mainly by thermal stresses and stress induced voiding (SIV).    front-end-of-line compatibility.
This is defined as the compatibility of the process during the production of the electrically active components. The bonding process must therefore be designed such that active components such as transistors which are already present on the structure wafers, are neither adversely affected nor damaged during the processing. Compatibility criteria include the purity of certain chemical elements (mainly in CMOS structures), mechanical and thermal loadability, mainly by thermal stresses.    low contamination.    no application of force, or application of force as low as possible.    temperature as low as possible, especially for materials with different coefficients of thermal expansion.
The reduction of the bond force leads to more careful treatment of the structure wafer and thus to a reduction of the failure probability by direct mechanical loading, especially when the insulating layers between the metallic conductors are made from so-called “low-k” materials.
Current bonding methods are designed primarily for high pressures and temperatures. Avoiding a high temperature is of essential importance for the welding of future semiconductor applications, since different materials with different coefficients of thermal expansion generate thermal stresses which cannot be ignored during heating and cooling processes. Furthermore, the diffusion of doping elements as the temperature rises is increasingly becoming a problem. The doped elements should not leave the intended three-dimensional region after the doping process. Otherwise, the physical properties of the circuits would fundamentally change. In the best case, this leads to deterioration, in the worst and most probable case to unserviceability of the component. Memories are very susceptible due to degradation of the dielectric and the associated shortened storage time during thermal processes. On the other hand, there are memories in which 3D technology is being increasingly used to raise the capacity and performance.
An advantage of this invention is a method for production of a permanent bond between two substrates with a bond force as high as possible at a temperature which is simultaneously as low as possible and/or at an average process time.
This advantage is achieved with the features of claims 1 and 6. Advantageous developments of the invention are given in the dependent claims. All combinations of at least two of the features given in the specification, the claims and/or the figures also fall within the framework of the invention. At the given value ranges, values which lie within the indicated boundaries will also be considered disclosed as boundary values and will be claimed in any combination.